Glossary entry (derived from question below)
Apr 6, 2007 08:35
17 yrs ago
1 viewer *
English term
clock slip
English to German
Tech/Engineering
Electronics / Elect Eng
Datenzugangsanordnung
"Either one half of one symbol ('0’ = '01' or '1' = '10') has been corrupted, resulting in a half-symbol error, or there has been a loss of synchronization due to a clock slip on the DIB."
Mein Übersetzungsversuch ohne das verflixte clock slip:
"Eine Hälfte eines Symbols ('0’ = '01' oder '1' = '10') wurde korruptiert, was zu dem Fehler führt, dass das Symbol nur aus einer Hälfte besteht, oder es fand aufgrund eines clock slip an der DIB ein Synchronisationsverlust statt."
Ich habe zwar die folgende englische Definition gefunden, aber das hilft mir leider nicht weiter:
"If timing between devices is not maintained, a condition known as clock slippage (clock slips) can occur. By definition, a clock slip is the repetition or deletion of a bit (or block of bits) in a synchronous data stream, due to a discrepancy in the read and write rates at a buffer. Slips arise because an equipment buffer store, or other mechanisms, cannot accommodate differences between the phases or frequencies of the incoming and outgoing signals. This occurs in cases where the timing of the outgoing signal is not derived from that of the incoming signal."
Mein Übersetzungsversuch ohne das verflixte clock slip:
"Eine Hälfte eines Symbols ('0’ = '01' oder '1' = '10') wurde korruptiert, was zu dem Fehler führt, dass das Symbol nur aus einer Hälfte besteht, oder es fand aufgrund eines clock slip an der DIB ein Synchronisationsverlust statt."
Ich habe zwar die folgende englische Definition gefunden, aber das hilft mir leider nicht weiter:
"If timing between devices is not maintained, a condition known as clock slippage (clock slips) can occur. By definition, a clock slip is the repetition or deletion of a bit (or block of bits) in a synchronous data stream, due to a discrepancy in the read and write rates at a buffer. Slips arise because an equipment buffer store, or other mechanisms, cannot accommodate differences between the phases or frequencies of the incoming and outgoing signals. This occurs in cases where the timing of the outgoing signal is not derived from that of the incoming signal."
Proposed translations
(German)
3 | Taktfehler |
Herbie
![]() |
Proposed translations
1 hr
Selected
Taktfehler
Das sollte es sein
4 KudoZ points awarded for this answer.
Comment: "Vielen Dank!"
Something went wrong...